1. Field of Invention
The present invention relates to methods for manufacturing semiconductor integrated circuits and to semiconductor integrated circuits manufactured by these methods. More particularly, the invention relates to semiconductor integrated circuits, such as gate arrays and embedded arrays, which include logic circuits designed to meet customer specifications.
2. Description of Related Art
In order to flexibly meet customer specifications, many semiconductor integrated circuits (ICs), such as gate arrays and embedded arrays, are used. In general, a plurality of transistors included in such ICs have source/drain regions of the same shape in basic cells arrayed with a certain pitch. Consequently, many of these transistors have source/drain regions which are larger than those required for obtaining necessary driving capabilities. However, if the size of a transistor is larger, the input capacitance of the transistor is also larger. Such a large input capacitance may cause a large electric current to flow, resulting in large noise or large consumption of electric power. Therefore, in order to decrease the input capacitance and the power consumption, it is desired that the size of each transistor be minimized.
For example, a large-scale logic circuit, which operates in synchronization with input clock signals, may be included in an IC. Such a logic circuit includes, for example, a clock tree circuit, in which a plurality of buffer circuits are combined, so that an input clock signal is branched out, and a register circuit, including a plurality of flip-flop circuits, which operate in synchronization with branched out clock signals.
FIG. 8 is a circuit diagram which shows an example of a circuit configuration of such a clock tree circuit. A clock tree circuit 100 is a combinational logic circuit in which plural stages of buffer circuits (four-stage buffer circuits 101, 102, 103, and 104 in FIG. 8) are combined. The buffer circuits 101, 102, 103, and 104 are arranged and connected in a form of a tree, from a top end to a bottom end. That is, the clock tree circuit 100 branches out an input clock signal into a plurality of output clock signals (64 clock signals in FIG. 8) having the same phase.
The clock tree circuit and the register circuit, for example, include transistors to which clock signals are input. Certain amounts of parasitic capacitance (not shown as a circuit element in a circuit diagram) are present between the gate and the drain, between the gate and the source, and between the source and the drain in the transistors. Among them, the parasitic capacitance, between the gate and the drain and between the gate and the source, correspond to the input capacitance of the transistor. Therefore, a circuit in which a large number of transistors are connected in parallel has large input capacitance.
In general, transistors that have large driving power are required for a combinational logic circuit like a clock tree circuit in which many transistors and long wiring are connected to the output. On the other hand, transistors that have small driving power are sufficient for a circuit in which a small number of transistors and short wiring are connected to the output, such as a buffer circuit at the last stage of a clock tree circuit and an output circuit for outputting to a sequential logic circuit, such as a register circuit. Consequently, if a layout is designed in a way that the source/drain regions of the transistors have the same size, the input capacitance of the latter transistors may become unnecessarily large.
Therefore, Japanese Unexamined Patent Application Publication No. 9-191095 discloses a semiconductor integrated circuit in which the transistor size is minimized so that the input capacitance is reduced. In the disclosed semiconductor integrated circuit, an impurity region (area) of each transistor formed on a semiconductor substrate can be changed. That is, after an impurity region is formed in accordance with the minimum driving capability required for each transistor, an interlayer insulating film is formed, openings are formed at predetermined positions of the interlayer insulating film, and a wiring layer to electrically be connected to the gate electrode and the impurity region through the openings is formed.
However, according to the above publication, a mask for forming a field insulating film and a mask for forming an impurity region must be prepared according to the size of each transistor, and thereby a great deal of effort is required in the design. It is also troublesome to cope with changes in the design.
The present invention has been provided in view of the circumstances described above. It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit in which the transistor size can be minimized by only changing one mask after the operation of a prototype is checked, and to provide a semiconductor integrated circuit manufactured by the manufacturing method.
According to a first aspect of the present invention, a method for manufacturing a semiconductor integrated circuit that includes a logic circuit having transistors includes the steps of:
forming a field insulating film having a first area in a predetermined region of a semiconductor substrate in order to manufacture a prototype semiconductor integrated circuit, the prototype semiconductor integrated circuit being usable to check whether a designed semiconductor integrated circuit operates accurately;
forming transistor gate insulating films and gate electrodes in predetermined regions of the semiconductor substrate for prototyping;
forming transistor impurity regions in predetermined regions surrounded by the field insulating film on the semiconductor substrate for prototyping;
forming an interlayer insulating film so as to cover at least the gate electrodes and the impurity regions;
forming openings at predetermined positions of the interlayer insulating film;
forming a wiring layer to electrically be connected to the gate electrodes and the impurity regions through the openings;
testing performance of the prototype semiconductor integrated circuit;
forming a field insulating film having a second area that is larger than the first area in a predetermined region of a new semiconductor substrate when the prototype semiconductor integrated circuit performs in a desired manner;
forming transistor gate insulating films and gate electrodes in predetermined regions of the new semiconductor substrate;
forming transistor impurity regions in predetermined regions surrounded by the field insulating film on the new semiconductor substrate;
forming an interlayer insulating film so as to cover at least the gate electrodes and the impurity regions on the new semiconductor substrate;
forming openings at predetermined positions of the interlayer insulating film on the new semiconductor substrate; and
forming a wiring layer to electrically be connected to the gate electrodes and the impurity regions through the openings of the new semiconductor substrate.
According to a second aspect of the present invention, a method for manufacturing a semiconductor integrated circuit that includes a logic circuit having transistors includes the steps of:
forming a field mask (field mask for prototyping) suitable for manufacturing a prototype semiconductor integrated circuit, the prototype semiconductor integrated circuit being usable to check whether a designed semiconductor integrated circuit operates accurately;
forming a field insulating film in a predetermined region of a semiconductor substrate using the field mask for prototyping;
forming transistor gate insulating films and gate electrodes in predetermined regions of the semiconductor substrate for prototyping;
forming transistor impurity regions in predetermined regions surrounded by the field insulating film on the semiconductor substrate for prototyping;
forming an interlayer insulating film so as to cover at least the gate electrodes and the impurity regions;
forming openings at predetermined positions of the interlayer insulating film;
forming a wiring layer to electrically be connected to the gate electrodes and the impurity regions through the openings;
testing the performance of the prototype semiconductor integrated circuit;
forming a field mask (field mask for shipment) suitable for manufacturing a semiconductor integrated circuit for shipment according to the results from the testing step;
forming a field insulating film in a predetermined region of a new semiconductor substrate using the field mask for shipment;
forming transistor gate insulating films and gate electrodes in predetermined regions of the new semiconductor substrate;
forming transistor impurity regions in predetermined regions surrounded by the field insulating film on the new semiconductor substrate;
forming an interlayer insulating film so as to cover at least the gate electrodes and the impurity regions on the new semiconductor substrate;
forming openings at predetermined positions in the interlayer insulating film on the new semiconductor substrate; and
forming a wiring layer to electrically be connected to the gate electrodes and the impurity regions through the openings of the new semiconductor substrate.
Herein, the logic circuit may include at least one of a combinational logic circuit, in which a plurality of buffer circuits are combined so that an input clock signal is branched out into a plurality of output clock signals, and a sequential logic circuit, in which a plurality of flip-flop circuits are combined so that input data signals are retained in synchronization with input clock signals.
Each step of forming the field insulating film, the gate insulating films, the gate electrodes, the impurity regions, the interlayer insulating film, the openings, and the wiring layer may sequentially be performed in accordance with a master slice process.
According to another aspect of the present invention, a semiconductor integrated circuit includes a plurality of basic cells arrayed with a certain pitch, the plurality of basic cells including a first group of basic cells having an active region with the a first area and a second group of basic cells having an active region with a second area smaller than the first area.
Herein, the first group of basic cells may constitute a combinational logic circuit and the second group of basic cells may constitute a sequential logic circuit.
According to the present invention, a prototype semiconductor integrated circuit is manufactured, and the circuit operation is tested. When the prototype semiconductor integrated circuit operates accurately, it is possible to minimize the transistor size by only changing the field mask. Therefore, by making a simple change, the input capacitance of the transistors can be decreased in response to the required driving capability.